Workshop Highlights:

This workshop provides a thorough background in the synthesis and optimization of digital system and circuits, and introduces the methodology to design a digital system from its C algorithm code to its FPGA (ASIC) implementation. The training focuses on the concepts underlying the digital synthesis and optimization, but complements with carefully designed hands-on labs to reinforce the introduced concepts. Not only introducing the general concepts, the workshop uses a specific hardware description language VHDL and a specific digital hardware platform FPGA to illustrate the application of the general synthesis and optimization concepts. In terms of VHDL, we go from basic concepts and syntax, through synthesis coding styles and guidelines, to design verification. In terms of FPGA, we introduce the FPGA architectures and EDA flow. The workshop concludes with a project which requires you to apply all the knowledge you have learned in the 3 days. In the major project, you will base on the provided C code for a MPEG decoder, and use the introduced synthesis and optimization methods to gradually refine the decoder C code to its FPGA implementation.

Workshop Objectives:

• To provide a complete understanding of the essential concepts of digital synthesis and optimization techniques used in EDA tools
• To give you practical experience of writing VHDL for synthesis and verification in a project-based environment using the latest tools.
• To give you practical experience of using FPGAs for the prototyping of your design projects in a project-based environment using the latest FPGAs and tools.

Pre-requisite:

Delegates should have a basic knowledge of digital hardware design and be familiar with their choice of operating system. Although some experience of a software language is useful, it is not essential. The workshop assumes no prior knowledge of VHDL and FPGA.

Workshop Structure

The workshop is based around a 3-day agenda. Most lectures have been followed with a lab to reinforce the concept you learned with hands-on experience.

Workshop Outline:

Days 1 Digital System Platforms and Specification

• Introduction to Digital System Design
• Platforms
• Hardware modeling overview
• Design flows
• Issues and Quality Metrics in Digital Circuit Design
• Functionality and robustness
• Performance
• Power and Energy Consumption
• Timing issues and metrics for sequential circuits
• FPGA architecture and EDA
• FPGA logic blocks
• FPGA routing networks
• State-of-the-art FPGA architectures
• FPGA EDA algorithms and methodology
• Graph Theory Basics
• Graphs
• Combinatorial optimization
• Graph optimization problems and algorithms
• Hardware Modeling
• Hardware modeling languages
• Abstract models
• Compilation and behavioral optimization
• FPGA prototyping hands-on
• VHDL description of a full adder
• Implementation of the full adder with an FPGA board

Day 2: Digital System Synthesis and Optimization

• Architectural-Level Synthesis and Optimization
• Circuit specification for architectural synthesis
• Scheduling
• Resource Biding
• Data-path synthesis
• Control-unit synthesis
• Logic-Level Synthesis and Optimization
• Two-level  
• Performance
• Power and Energy Consumption
• Timing issues and metrics for sequential circuits
• Physical Synthesis
• Technology Mapping
• Floorplanning
• Placement
• Routing

Day 3: Advanced VHDL and FPGA with a Project

• VHDL language revisit
• Design units and main language concepts
• Logical and relational operators, concatenation and array slices
• Processes and sequential statements
• Concurrent statements and equivalent processes
• Simulation execution, sensitivity lists and wait statements
• Variables and variable use
• Arithmetical operators, overloading and arithmetic packages
• Coding styles for efficient hardware synthesis
• Synthesis of variables
• Types, sub-types, closely-related types and type conversions
• FSM’s and state vector encoding
• FSM coding styles and templates
• Coding styles for test benches, RTL and behavioral code
• Coding styles and strategies for generating test stimulus
• A MPEG decoder project that starts from its C code to FPGA prototyping.
• MPEG decoder C code verification
• (Manual) Behavioral synthesis of decoder C code to RTL VHDL code
• Verification of the generated RTL VHDL code
• Designing the interfaces for the decoder with RTL VHDL code.
• Implement the overall MPEG decoder in FPGA

Workshop Labs

The labs have been designed to complement the lecture contents of the workshop. The last lab is a design project that needs you to use all the knowledge that you have learned in the workshop. The first few labs get you familiar with the tools you are using and the basic steps involved in simulating, synthesizing and implementing a small design. Subsequent labs are based upon design modeling, verification issues and performance tuning that are typically encountered in a real world design project.

The lab sessions include

• Familiarization with digital system simulation and synthesis tools
• Xilinx ISE and ModelSim tool flow
• State machine design
• Verification using VHDL file I/O based test benches
• Verification of C algorithms
• FPGA prototyping of a full adder
• A major project includes the VHDL modeling and FPGA prototyping of a MPEG decoder from its C algorithm.