Course Highlights:

Larger and faster Systems-on-Chips employ multiple clock domains on the same die for several reasons: Communications with external real-time or pre-defined clocks require chips to incorporate multiple, unrelated clock frequencies; it is more economical in very large chips to break down the system into independently clocked domains, saving some of the power required for clock distribution; and dynamic scaling of voltage and frequency creates multiple clock/voltage domains. Interfaces among different clock domains are problematic and are only partly supported by commercial EDA tools. As a result, synchronization problems are sometimes discovered only in working silicon, and even then they are hard and expensive to correct.

About the Course

The course teaches the science, engineering and art of synchronization. We define the problems, survey existing solutions, study the best designs, and learn how to select the better synchronizer for each purpose. We review clocking in digital chips, study the required theoretical basics, learn how to understand synchronization problems, identify them, create reliable solutions, and verify their correctness. We consider SoC / ASIC and FPGA, mostly at the logical level. Implications on physical design are briefly reviewed. We also review voltage domains, power gating, voltage scaling and their effect on clock domains and synchronization.

Who Should Attend:

• VLSI/ASIC/SoC/FPGA design engineers, architects and managers engaged in the design of advanced SoC
• VLSI/ASIC/SoC/FPGA CAD engineers and developers
• Academic researchers, university professors, and graduate students interested in advanced SoC design

Course Outline:

Day One: We review the synchronization problem, examine conventional clock distribution networks and consider the issues faced while designing them. Delay variations, technology trends and scaling are discussed. Methods of overcoming some clocking and timing problems are reviewed. Synchronization failures and metastability are studied closely, including basics of latches, flip-flops and the importance of race-free design.

• Introduction
  • Problem Definition and Motivation
  • Course description
    
    
• Clock Distribution Networks
  • Problem Definition
  • What’s Ahead: The technology roadmap
  • ASIC / SoC vs. Full-Custom Design Methodologies
  • Standard Clock Trees for SoCs and FPGA
  • Min-Delay and Max-Delay Problems
  • Data Delay Insertion
  • Delay Line Circuits
  • Clock Delay Insertion
  • Clock Tuning
  • Unbalanced Tunable Clock Distribution Networks
  • High Performance Clock Trees
  • Passive and Active Deskew in Clock Trees
  • Local Clock Generation with Tunable Frequencies
    
    
• Metastability and Synchronization Failures
  • Metastability
  • Latches and Flip-Flops
  • Measuring Metastability
  • Probability and MTBF
  • Synchronizer Circuits
  • Symmetric Booster Synchronizer
  • Latency and Settling Time
  • Simulating Metastability
  • Special Synchronizer Circuits

Day Two: We study the various available synchronizers and learn when it is best to apply each one. Common synchronization errors are discussed and presented, so that we can avoid them. Commercial EDA tools for formal verification of synchronizers are examined and verification with more standard tools is discussed.

• Synchronization of Asynchronous Clock Domains
  • Control Synchronizers
  • Formal Specification Using STG
  • Data Validity of Synchronizers
  • Push Synchronizers
  • Timing Assumptions
  • Pull and Push-Pull Synchronizers
  • Fast Synchronizers
  • Shared Latch Synchronizers
  • FIFO Synchronizers
  • Reset Synchronization
  • Clock Gating and Selection Synchronizers
  • Scan Insertion Synchronizer
  • Mutual Exclusion and Arbiters
    
• Common Synchronization Errors
  • Avoiding Synchronization
  • One flop Synchronizers
  • Sneaky and Greedy Paths
  • Half Protocol
  • Async Clear
  • DFT Leak
  • Pulse Synchronizers
  • Slow-to-Fast Synchronizers
  • Metastability Blocker
  • Parallel, Shared Latch, and Conservative Synchronizers
  • Metastability Filtering Latch
  • Patented Circuits for Fast Resolution
  • Patented Circuits for Pre-Sampling
  • Shaker Latch Synchronizer
  • Dual Shaker Synchronizer
    
    
• Formal Verification of Synchronizers
  • Identifying Domain Crossings
  • Structural Verification
  • Sorting the Crossings
  • Grouping Synchronizers
  • Connecting Bi-Directional Protocols
  • Recognizing the Synchronizers
  • Employing Formal Tools
  • Functional Verification
  • Data Verification
  • Manual Verification

Day Three: We consider aggressive and complex synchronizers for communications between two related clock domains, whose frequencies are the same or multiples of each other. Methods for long on-chip interconnects between unrelated clock domains are reviewed. We conclude with Globally Asynchronous Locally Synchronous (GALS) SoCs and study novel and efficient approaches to multiple clock domains that may be required for SoCs using advanced processes.

• Multi-Synchronous and Periodic Synchronizers
  • Mesochronous / Multisync Synchronization
  • Delay Variations
  • Data Delay Synchronizers
  • Conflict Detection
  • Dual Data Delay Synchronizers
  • Clock Delay Synchronizers
  • FIFO Synchronizers
  • Clock Edge Synchronizers
  • Periodic Domains Synchronizers
  • Predictive Synchronizers
  • Fixed Lag Synchronizers
    
    
• Multi-Synchronous and Asynchronous Long Interconnect
  • Definition of Long Interconnects
  • Point-to-Point, Buses and Networks on Chip
  • Source-Synchronous and Adaptive-Clocked Interconnect
  • Data Encoding: Dual rail and 1-of-4
  • Four- and Two-Phase Protocols
  • Asynchronous Interconnect
  • Dual Rail and 1-of-4 Interconnect
  • Two-Phase Dual Rail Interconnect
  • Fast Serial Interconnect
  • Asynchronous FIFO
  • Mixed-Timing FIFO
  • 4-Phase, 2-Phase Pipeline Synchronizer
  • Fast General Synchronizer
    
    
• Multi-Clock Domain and GALS SoC
  • Why MCD Chips
  • Synchronizer-Based GALS
  • Arbitrated Stoppable Clocks
  • Wrappers and Asynchronous Ports
  • GALS Methodologies
  • Handshake Stoppable Clocks
  • Desynchronization
  • Synchronization in Networks on Chips (NoC)
  • Dynamic Voltage and Frequency Scaling
    
    
• Multiple voltage domains
  • Definitions
  • Sources of Multiple Voltages
  • Level Shifting
  • Combining Voltage and Clock Domains
  • Floor-Plan and Layout Constraints
  • Varying Clock Frequency with Voltage
  • Architectural Implications of Multiple Voltage Domains
  • Dynamic Voltage and Frequency Scaling
  • Voltage Scaling versus Voltage and Frequency Scaling
  • Global versus Multi-Domain Scaling
  • Methods of DVFS
  • Architectural Implications of DVFS
    
    
• Conclusions and Summary